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| Preliminary Information X24C01A 1K X24C01A Serial E2PROM DESCRIPTION 128 x 8 Bit FEATURES * * * * * * * * 2.7V to 5.5V Power Supply Low Power CMOS --Active Current Less Than 1 mA --Standby Current Less Than 50 A Internally Organized 128 x 8 Self Timed Write Cycle --Typical Write Cycle Time of 5 ms 2 Wire Serial Interface --Bidirectional Data Transfer Protocol Four Byte Page Write Operation --Minimizes Total Write Time Per Byte High Reliability --Endurance: 100,000 Cycles --Data Retention: 100 Years New Hardwire - Write Control Function The X24C01A is a CMOS 1024 bit serial E2PROM, internally organized 128 x 8. The X24C01A features a serial interface and software protocol allowing operation on a simple two wire bus. Three address inputs allow up to eight devices to share a common two wire bus. Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Available in an eight pin DIP and SOIC package. FUNCTIONAL DIAGRAM (8) VCC (4) VSS (7) WC START CYCLE (5) SDA START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER +COMPARATOR XDEC E2PROM 32x32 H.V. GENERATION TIMING & CONTROL (6) SCL (3) A2 (2) A1 (1) A0 LOAD INC WORD ADDRESS COUNTER R/W YDEC 8 CK PIN DOUT ACK 3841 FHD F01 DATA REGISTER DOUT (c) Xicor, 1991 Patents Pending 3841-1 1 Characteristics subject to change without notice X24C01A PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Guidelines for Calculating Typical Values of Bus Pull-Up Resistors graph. Address (A0, A1, A2) The address inputs are used to set the least significant three bits of the seven bit slave address. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven to VSS or to VCC. WRITE CONTROL (WC) The Write Control input controls the ability to write to the device. When WC is LOW (tied to VSS) the X24C01A will be enabled to perform write operations. When WC is HIGH (tied to VCC) the internal high voltage circuitry will be disabled and all writes will be disabled. DEVICE OPERATION The X24C01A supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X24C01A will be considered a slave in all applications. A0 A1 A2 VSS 1 2 3 4 X24C01A DIP/SOIC 8 7 6 5 VCC WC SCL SDA PIN CONFIGURATION 3841 FHD F02 PIN NAMES Symbol A0-A2 SDA SCL WC VSS VCC Description Address Inputs Serial Data Serial Clock Write Control Ground +5V 3841 PGM T01 Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C01A continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. 2 X24C01A Figure 1. Data Validity SCL SDA DATA STABLE DATA CHANGE 3841 FHD F05 Figure 2. Definition of Start and Stop SCL SDA START BIT STOP BIT 3841 FHD F06 Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24C01A to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3. Figure 3. Acknowledge Response From Receiver SCL FROM MASTER The X24C01A will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24C01A will respond with an acknowledge after the receipt of each subsequent eight bit word. In the read mode the X24C01A will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24C01A will continue to transmit data. If an acknowledge is not detected, the X24C01A will terminate further data transmissions. The master must then issue a stop condition to return the X24C01A to the standby power mode and place the device into a known state. 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE 3841 FHD F07 3 X24C01A DEVICE ADDRESSING Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see Figure 4). For the X24C01A this is fixed as 1010[B]. Figure 4. Slave Address DEVICE TYPE IDENTIFIER 1 0 1 0 A2 A1 A0 R/W Following the start condition, the X24C01A monitors the SDA bus comparing the slave address being transmitted with its slave address (device type and state of A0, A1 and A2 inputs). Upon a correct compare the X24C01A outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24C01A will execute a read or write operation. WRITE OPERATIONS Byte Write For a write operation, the X24C01A requires a second address field. This address field is the word address, comprised of eight bits, providing access to any one of the 128 words of memory. Note: the most significant bit is a don't care. Upon receipt of the word address the X24C01A responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24C01A begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24C01A inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence. DEVICE ADDRESS 3841 FHD F08 The next three significant bits address a particular device. A system could have up to eight X24C01A devices on the bus (see Figure 10). The eight addresses are defined by the state of the A0, A1 and A2 inputs. The last bit of the slave address defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operation is selected. Figure 5. Byte Write S T BUS ACTIVITY: A R MASTER T SDA LINE BUS ACTIVITY: X24C01A S A C K SLAVE ADDRESS WORD ADDRESS DATA S T O P P A C K A C K 3841 FHD F09 Figure 6. Page Write S T BUS ACTIVITY: A R MASTER T SDA LINE BUS ACTIVITY: X24C01A S A C K A C K A C K A C K A C K 3841 FHD F10 SLAVE ADDRESS WORD ADDRESS n DATA n DATA n-1 DATA n+3 S T O P P NOTE: In this example n = xxxx 0000 (B); x = 1 or 0 4 X24C01A Page Write The X24C01A is capable of an four byte page write operation. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to three more words. After the receipt of each word, the X24C01A will respond with an acknowledge. After the receipt of each word, the two low order address bits are internally incremented by one. The high order five bits of the address remain constant. If the master should transmit more than four words prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence. Acknowledge Polling The disabling of the inputs, during the internal write operation, can be used to take advantage of the typical 5 ms write cycle time. Once the stop condition is issued to indicate the end of the host's write operation the X24C01A initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the X24C01A is still busy with the write operation no ACK will be returned. If the X24C01A has completed the write operation an ACK will be returned and the master can then proceed with the next read or write operation (See Flow 1). READ OPERATIONS Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read and sequential read. It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. 3841 FHD F11 Flow 1. ACK Polling Sequence WRITE OPERATION COMPLETED ENTER ACK POLLING ISSUE START ISSUE SLAVE ADDRESS AND R/W = 0 ISSUE STOP ACK RETURNED? YES NEXT OPERATION A WRITE? YES ISSUE BYTE ADDRESS NO NO ISSUE STOP PROCEED PROCEED 5 X24C01A Current Address Read Internally the X24C01A contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. Upon receipt of the slave address with R/W set to one, the X24C01A issues an acknowledge and transmits the eight bit word during the next eight clock cycles. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 7 for the sequence of address, acknowledge and data transfer. Random Read Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition, and the slave address followed by the word address it is to read. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the X24C01A and then by the eight bit word. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 8 for the address, acknowledge and data transfer sequence. Figure 7. Current Address Read S T BUS ACTIVITY: A R MASTER T SDA LINE BUS ACTIVITY: X24C01A S A C K DATA 3841 FHD F12 SLAVE ADDRESS S T O P P Figure 8. Random Read S T BUS ACTIVITY: A R MASTER T SDA LINE BUS ACTIVITY: X24C01A S A C K A C K S T A R T S A C K DATA n 3841 FHD F13 SLAVE ADDRESS WORD ADDRESS n SLAVE ADDRESS S T O P P 6 X24C01A Sequential Read Sequential Read can be initiated as either a current address read or random access read. The first word is transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires additional data. The X24C01A continues to output data for each acknowledge received. The read operation is terminated by the master, by not responding with an acknowledge and by issuing a stop condition. Figure 9. Sequential Read SLAVE BUS ACTIVITY: ADDRESS MASTER SDA LINE BUS ACTIVITY: X24C01A A C K DATA n DATA n+1 DATA n+2 DATA n+x 3841 FHD F14 The data output is sequential, with the data from address n followed by the data from n + 1. The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 127), the counter "rolls over" to address 0 and the X24C01A continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowledge and data transfer sequence. A C K A C K A C K S T O P P Figure 10. Typical System Configuration VCC SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER 3841 FHD F15 7 X24C01A ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias .................. -65C to +135C Storage Temperature ....................... -65C to +150C Voltage on any Pin with Respect to VSS ............................... -1.0V to +7V D.C. Output Current ............................................ 5 mA Lead Temperature (Soldering, 10 Seconds) ............................. 300C RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Military Min. 0C -40C -55C Max. 70C +85C +125C 3841 PGM T02 *COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Supply Voltage X24C01A X24C01A-3.5 X24C01A-3 X24C01A-2.7 Limits 4.5V to 5.5V 3.5V to 5.5V 3V 5.5V 2.7V to 5.5V 3841 PGM T03 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified) Limits Symbol lCC1 Parameter Power Supply Current (read) Power Supply Current (write) Standby Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Min. Max. 1 Units mA Test Conditions SCL = VCC x 0.1/VCC x 0.9 Levels @ 100 KHz, SDA = Open, All Other Inputs = GND or VCC - 0.3V SCL = VCC x 0.1/VCC x 0.9 Levels @ 100 KHz, SDA = Open, All Other Inputs = GND or VCC - 0.3V SCL = SDA = VCC - 0.3V, All Other Inputs = GND or VCC, VCC = 5.5V SCL = SDA = VCC - 0.3V, All Other Inputs = GND or VCC, VCC= 3.3V + 10% VIN = GND to VCC VOUT = GND to VCC ICC2 2 mA ISB(1) ISB(1) ILI ILO VlL(2) VIH(2) VOL 50 30 10 10 VCC x 0.3 VCC + 0.5 0.4 A A A A V V V -1.0 VCC x 0.7 IOL = 3 mA 3841 PGM T04 CAPACITANCE TA = 25C, f = 1.0MHZ, VCC = 5V Symbol CI/O(3) CIN(3) Test Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL, WC) Max. 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V 3841 PGM T06 Notes: (1) Must perform a stop command prior to measurement. (2) VIL min. and VIH max. are for reference only and are not tested. (3) This parameter is periodically sampled and not 100% tested. 8 X24C01A A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 3841 PGM T07 EQUIVALENT A.C. LOAD CIRCUIT 5.0V 1533 Output 100pF 3841 FHD F17 A.C. CHARACTERISTICS LIMITS (Over recommended operating conditions unless otherwise specified) Read & Write Cycle Limits Symbol fSCL TI tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH Parameter SCL Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out Valid Time the Bus Must Be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Min. 0 0.3 4.7 4.0 4.7 4.0 4.7 0 250 Max. 100 100 3.5 Units KHz ns s s s s s s s ns s ns s ns 3841 PGM T08 1 300 4.7 300 POWER-UP TIMING Symbol tPUR(4) tPUW(4) Bus Timing tF SCL tSU:STA SDA IN tAA SDA OUT tDH tBUF tHD:STA tHD:DAT tSU:DAT tSU:STO tHIGH tLOW tR Parameter Power-Up to Read Operation Power-Up to Write Operation Max. 1 5 Units ms ms 3841 PGM T09 3841 FHD F03 Note: (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. 9 X24C01A WRITE CYCLE LIMITS Symbol tWR(6) Parameter Write Cycle Time Min. Typ.(5) 5 Max. 10 Units ms 3841 PGM T10 The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24C01A Write Cycle Timing bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. SCL SDA 8th BIT WORD n ACK tWR STOP CONDITION START CONDITION X24C01A ADDRESS 3841 FHD F04 Notes: (5) Typical values are for TA = 25C and nominal supply voltage (5V). (6) tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device requires to perform the internal write operation. Guidelines for Calculating Typical Values of Bus Pull-Up Resistors 120 RESISTANCE (K) VCC MAX =1.8K IOL MIN tR CBUS SYMBOL TABLE WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance 100 80 60 40 20 0 0 RMIN = RMAX = MAX. RESISTANCE MIN. RESISTANCE 20 40 60 80 100 120 3841 FHD F16 BUS CAPACITANCE (pF) 10 X24C01A PACKAGING INFORMATION 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 0.430 (10.92) 0.360 (9.14) 0.260 (6.60) 0.240 (6.10) PIN 1 INDEX PIN 1 0.300 (7.62) REF. 0.060 (1.52) 0.020 (0.51) HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL SEATING PLANE 0.150 (3.81) 0.125 (3.18) 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41) 0.110 (2.79) 0.090 (2.29) 0.015 (0.38) MAX. 0.325 (8.25) 0.300 (7.62) TYP. 0.010 (0.25) 0 15 NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 11 X24C01A PACKAGING INFORMATION 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.150 (3.80) 0.158 (4.00) PIN 1 INDEX 0.228 (5.80) 0.244 (6.20) PIN 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7 0.053 (1.35) 0.069 (1.75) 0.050 (1.27) 0.004 (0.19) 0.010 (0.25) 0.010 (0.25) X 45 0.020 (0.50) 0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.41) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESIS IN MILLIMETERS) 12 X24C01A ORDERING INFORMATION X24C01A Device P T -V VCC Limits Blank = 5V 10% 3.5 = 3.5V to 5.5V 3 = 3.3 10% Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C M = Military = -55C to +125C Package P = 8-Lead Plastic DIP S8 = 8-Lead SOIC LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 13 |
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